Storage of data and instructions in a memory structure is necessary to virtually any data processor application. For this reason, among others, the development of high-performance memory structures has accompanied the development of data processing circuits and integrated microprocessors in particular. Thus, as integration density and processing power of microprocessors has increased, the same attributes have been sought in storage per chip as well as to increase speed of the memory structure.
Memory structures are often considered to fall into one of two groups: static memories and dynamic memories.
Highest memory read access speed is achieved by static random access memories (SRAMs). In such static memories, the data are stored in a bistable latch (or flip-flop) comprised of active circuits. Therefore, no time is required for either refresh or other operations to restore charge after reading.
While bipolar, n-channel, or p-channel SRAMs are not generally regarded as relying on stored charge (since, in normal operations, any charge lost through reading or leakage is continually replaced by operation of the active bistable circuit there), when implemented with complementary field effect transistors, voltages present on various nodes, such as the drain nodes, may cause storage of charge in a depletion region within or around a portion of the field effect transistors.
If an energetic particle from the environment, such as an alpha-particle, strikes a junction, such as the drain junction, surrounded by such a depletion region, electrons and holes will be generated within the underlying body of semiconductor material and will collect along the boundary of the depletion region. If the energetic particle strikes a junction (e.g. the drain junction of an N-type transistor) holding a charge in a depletion region, the size of the depletion region, the stored charge, and the voltage across the junction will be reduced by the charge perturbation. Similarly, if an energetic particle strikes a junction of a P-type transistor at low voltage, the charge perturbation will cause the stored charge and the voltage to be increased. Thus, if the charge perturbation is sufficiently large, the stored logic state may be reversed. This is commonly referred to as a "soft error" since the error is not due to a hardware defect and the cell will operate normally thereafter (although it may contain erroneous data until rewritten). Soft errors are increased by stand-by operation at reduced voltage.
Dynamic random access memories (DRAMs) offer the greatest potential for reduction of cell size since a DRAM cell typically includes only one transistor and a smaller storage capacitance. Therefore, DRAMs have the potential for the greatest amount of storage per chip. Power consumption is also relatively low. On the other hand, a storage capacitor is used as the storage mechanism and since some degree of leakage is unavoidable in any storage structure, the stored charge representing the stored data must be refreshed periodically. This requirement for periodic refreshing of stored data causes some periods during which the DRAM cell is not available to be read and thus increases the average cycle time and effectively reduces the speed of the response of the memory.
If an energetic particle from the environment, such as an alpha-particle, strikes a junction, such as the drain junction of a DRAM cell, electrons and holes will be generated near the drain region causing leakage current to flow to the ground. The leakage current will discharge the storage capacitor. Generally, when the storage capacitor is charged, the DRAM cell is at a high logic level and when the storage capacitor is discharged, the DRAM is at a low logic level. Accordingly, an alpha-particle strike can cause the logic level of the DRAM cell to change from a high logic level to a low logic level. Therefore, there will be a loss of data stored, an error, in the DRAM cell between refreshed cycles.
Alpha-particles can induce similar soft error problems in semiconductor memory cells that are embedded in microprocessor or other logic circuits.
A performance parameter of an SRAM cell is the critical charge, Q.sub.c, which is the amount of charge that will cause a logic state reversal of the latch by causing a sufficiently large voltage disturbance. In the case of a DRAM cell, Q.sub.c is the amount of charge which will cause a logic state reversal by causing a sufficiently large leakage current to flow that will discharge the storage capacitor. Unfortunately, both miniaturization and lowered operating voltage (for example, the migration to 3.3 volt and beyond devices) of SRAM and DRAM cells with higher integration densities and/or lowered operating voltages also reduce the value of Q.sub.c for stable operation of the memory cells. Accordingly, SRAMs and DRAMs have become increasingly vulnerable to soft errors. Many attempts have been made to simulate the alpha-particle strikes in memory cells in efforts to determine their robustness to alpha-particle induced soft errors.
However, many of these attempts to determine the robustness of a device to alpha-particle induced soft errors involve tedious and burdensome methods to generate alphaparticles. Focused alpha-particle sources, such as a lead-encased source, are very expensive, huge in size, and considered hazardous due to radioactivity. A focused alpha-particle beam requires a room-sized accelerator and comprehensive shielding. Therefore, such alpha-particle sources are not allowed, nor are they of a size that can be accommodated, in a typical semiconductor manufacturing facility or laboratory where the determination of device robustness to alpha-particles would normally be done. Where smaller alpha-particle sources are available, they are subject to OSHA (Occupational Safety and Health Agency) licensing. In both cases, the sources provide radiation hazard risk.
Another drawback of using a conventional alpha-particle source is the inability to control the direction of strike of the alpha-particles. The alpha-particles travel in random directions and are not be controllable so that they cannot be directed to strike predetermined locations, such as the drain junctions of a transistor in a memory cell. Absent such directional control, the resulting alpha-particle induced soft errors can not be reproduced. This makes duplication of alpha-particle effects unrepeatable.
An inexpensive method and apparatus having a smaller size that would simulate an alpha-particle strike in predetermined areas of a memory cell with directional control and repeatable results, has long been sought, but has eluded those skilled in the art.